1. Field of the Invention
This invention relates to a semiconductor device and a method of producing the semiconductor device and more particularly, relates to a semiconductor device having a gallium arsenide (GaAs) crystalline thin film on a silicon (Si) substrate, and a method of producing the same.
GaAs is used to obtain a higher speed operation than obtainable with Si, and has a light emission function enabling it to be used for a LED or Laser etc. Nevertheless, it is not easy to obtain a large diameter wafer of GaAs, and the mechanical strength thereof is low, and thus in practice GaAs is not used as much as Si.
In view of the above, attempts have been made to form a GaAs substrate on a Si substrate having a large diameter, which can be easily obtained and has a superior mechanical strength, and to form a device on the surface of the GaAs substrate.
2. Description of the Related Art
As shown in FIG. 1, when a GaAs crystalline layer 2 is formed directly on a Si substrate 1 a number of defects such as strain and dislocation, etc., occur due to the difference of the lattice constants thereof or the thermal expansion coefficients at the interface between the GaAs crystalline layer 2 and the Si substrate 1, and those defects are propagated to the upper layer, as denoted by line 5. Thus, a device having good electrical properties cannot be obtained. Namely, when for example a MESFET or a HEMT, etc. is formed, the threshold voltage is varied. Therefore, a method of directly reducing the crystal defects of about 10.sup.7 to about 10.sup.8 /cm.sup.2 existing in the GaAs crystalline layer also has been considered.
To reduce the crystal defects, for example, after a GaAs crystalline layer is grown on a Si substrate, a thermal cycle annealing has been carried out in which, for example, a heat treatment at a temperature of 200.degree. C. for 10 min., and subsequently, at a temperature of 800.degree. C. for 10 min., is repeated. Also, to reduce the crystal defects, a half-thick GaAs layer for a desired thick GaAs layer is first grown, and subsequently, the above-mentioned thermal cycle annealing is effected and then a GaAs layer is formed as the remaining half-thick layer.
Nevertheless, in the above-mentioned GaAs crystal defect reduction process using the thermal cycle annealing, it is difficult to lower the crystal defect density to approximately a 1.times.10.sup.6 /cm.sup.2 level, at which there is no influence on the electrical properties of an element.
Further, as a method of forming a GaAs layer on a Si substrate, it is well known that a buffer layer of Ge having a lattice constant close to that of GaAs can be formed on the Si substrate, and a GaAs layer can be formed on the buffer layer. When the buffer layer of Ge is formed on a Si substrate, a dislocation is often generated at the Si/Ge interface, due to approximately a four percent difference of the lattice constants of the Si and Ge, and thus it is difficult to lower the crystal defect density of GaAs to 1.times.10.sup.8 /cm.sup.2 or less.